1. Field
Example embodiments relate to a semiconductor memory device and a method of fabricating the same, and more particularly, to a semiconductor memory device and a method of fabricating the semiconductor memory device in which the generation of dishing during planarization of a peripheral circuit region is suppressed or minimized.
2. Description of the Related Art
Flash memory is a semiconductor memory device which has a specific type of an electrically erasable and programmable read-only memory (EEPROM). A typical flash memory includes a memory cell region having a plurality of memory cells which include floating gates and may be electrically erased and reprogrammed.
In the peripheral circuit region adjacent to the memory cell region, a driving circuit for driving the memory cells, a logic circuit for processing the information of the memory cells, and other devices are arranged. For example, memory cell strings may be provided in the memory cell region, and various driving circuits and logic circuits, which include active devices, e.g., transistors, or passive devices, e.g., resistors and capacitors, may be provided in the peripheral circuit region in order to implement a NAND flash device.
Typically, to manufacture such a memory device, first, an isolation film is formed in a semiconductor substrate to define an active area of a memory cell region and an active area of a peripheral circuit region. Thereafter, an insulation film, e.g., a silicon oxide film, is formed on the active areas, and a conductive film is deposited on the insulation film. Then, the conductive film may be planarized by performing a chemical mechanical polishing (CMP) process until an upper surface of the isolation film is exposed.
After the CMP process, a portion of the conductive film on the active area of the peripheral circuit region may be over-etched due to a difference between pattern densities of the memory cell region and the peripheral circuit region, resulting in dishing in the peripheral circuit region. In addition, a step difference between the memory cell region and the peripheral circuit region may be caused. In particular, for flash memory devices, a distance between memory cells is reduced according to the scaling down of the integrated devices, and, therefore, the thickness of a floating gate gradually decreases to reduce interference between memory cells. Consequently, the difference between the pattern densities of the memory cell region and the peripheral circuit region increases and, therefore, over-etching of the peripheral circuit region during the CMP process limits considerably the advance in capacity and integration of flash memory devices.
Due to over-etching caused by the CMP process, a portion of the insulation film below the conductive film in the peripheral circuit region is exposed, or the active area of the peripheral circuit region is exposed, which may lead to a reduction of the reliability of the semiconductor memory device and broad scattering of the device performance. The step difference between the memory cell region and the peripheral circuit region which is caused by the CMP process may impede securing a sufficient defocus margin in a subsequent process, e.g., a photolithography step for forming an interlayer insulation film and a wiring layer. To address these problems, a technique of reducing the difference between the pattern densities of the memory cell region and the peripheral circuit region by increasing the width of an isolation film in the peripheral circuit region has been proposed. However, this technique is not suitable for improving the integration of memory devices.